CV

Contact Information

Name Samit Shahnawaz Miftah
Professional Title Research Assistant
Email miftas@rpi.edu
Location 110 8th Street, Troy, NY 12180

Professional Summary

Samit Shahnawaz Miftah is a PhD researcher in Computer and Systems Engineering at Rensselaer Polytechnic Institute, specializing in hardware security, formal verification, and AI-driven design automation. With 10 peer-reviewed publications across top venues including IEEE MICRO, ACM/IEEE DAC, and IEEE TCAD, his work advances automated and intelligent methodologies for securing next-generation hardware systems. He is also a two-time top finisher at Hack@DAC — the world’s premier hardware security competition — and a CSAW AI Hardware Attack Challenge awardee.

Education

Awards

  • 2025
    Second Prize, Hack@DAC 2025
    Hack@DAC 2025

    Awarded for achieving second place in the Hack@DAC 2025 hardware security competition, demonstrating exceptional skills in finding and exploiting vulnerabilities in hardware systems.

  • 2025
    Third Prize, CSAW AI Hardware Attack Challenge 2025
    CSAW AI Hardware Attack Challenge 2025

    Awarded for achieving third place in the CSAW AI Hardware Attack Challenge 2025, demonstrating exceptional skills in finding and exploiting vulnerabilities in hardware systems.

  • 2024
    Third Prize, Hack@DAC 2024
    Hack@DAC 2024

    Awarded for achieving third place in the Hack@DAC 2024 hardware security competition, demonstrating exceptional skills in finding and exploiting vulnerabilities in hardware systems.

Publications

Skills

Programming Languages: Python, C/C++, TCL, SystemVerilog, Verilog, Chisel, VHDL
Tools: Xilinx - Vivado, Vitis HLS; Cadence - Virtuoso, Genus, Innovas, Xcelium, JasperGold; Synopsys - VCS, Design vision, Spyglass Lint; SymbiYosys, SMT-solver (Microsoft z3-Solver)
Frameworks: Universal Verification Methodology (UVM), Chipyard, Gem5, Linux, Git, LLM models (LangChain); Xilinx FPGA Boards, Raspberry Pi, Arduino

Languages

Bengali : Native speaker
English : Fluent

Interests

Computer Architecture and Hardware Security: Hardware Security, Hardware Verification, Computer Architecture, VLSI Design, Hardware Fuzzing, Formal Verification, AI-driven Design Automation

Projects

  • SpecGuard: Token-Efficient LLM-Based SVA Generation

    This project explores the application of Large Language Model agents for generating SystemVerilog assertions, aiming to improve the efficiency and effectiveness of hardware verification processes.

    • Challenge: LLM-based SVA generation collapses on large RTL due to token exhaustion, unstructured context, and frequent syntactic/semantic errors in generated assertions.
    • Developed SpecGuard – distills RTL into AST skeletons and facts cards so the model’s budget goes to assertion formulation, not design comprehension; achieves up to 987× higher functional coverage and 97% lower tokens-per-covered-event vs. state-of-the-art on 11 NVDLA/Coral NPU designs.
  • FlowFixer: Control-Flow-Based Automatic RTL Program Repair

    This project focuses on developing techniques for automatic program repair, leveraging generative AI and formal methods to identify and fix bugs in software systems.

    • Challenge: Hardware repair remains manual despite verification tools – localization heuristics misfire, rule-based tools cannot generalize, and naive LLM repair hallucinates without CFG-level context.
    • Developed FlowFixer – CFG/AST-driven bifurcated repair engine routes structural bugs to deterministic templates and complex flaws to a ReAct LLM agent; multi-tiered validation funnel with QoR scoring selects the minimal-area patch. Repairs 33% more bugs than RTL-Repair and 60% more than CirFix across 32 benchmarks.
  • CHoRD: Joint Scheduling and Data Placement for Chiplet-Based GPUs

    This project investigates the optimization of scheduling and data placement in chiplet-based GPU architectures, aiming to enhance the performance of deep neural network inference by reducing inter-chiplet NUMA traffic.

    • Challenge: Existing chiplet-GPU approaches optimize scheduling or placement independently, causing sustained inter-chiplet NUMA traffic that degrades DNN inference performance.
    • Mentoring a graduate student developing CHoRD – a compiler-assisted, profile-guided framework for joint kernel scheduling and data placement; achieves 2.94× geo-mean speedup over round-robin and 1.66× over placement-only baseline across 9 CNN/transformer workloads.