work SpecGuard A four-stage pipeline for generating, validating, and mutation-testing SystemVerilog Assertions — combining deterministic RTL analysis with LLM-based semantic validation for token efficiency. SymbFuzz Coverage-directed RTL fuzzer that combines random simulation with bounded model checking to reach hard-to-hit register states and coverage bins, then replays witness traces against a simulator. course AI Accelerator (Advanced VLSI) Parameterized TPU-style INT8 matrix-multiply accelerator in SystemVerilog for Xilinx Artix-7 — output-stationary systolic array with pluggable DSP, LUT-only, and approximate multipliers; 6.8 GMAC/s peak.