Publications

2026

1. PoSyn: Secure Power Side-Channel Aware Synthesis

   Amisha Srivastava, Samit S. Miftah, Hyunmin Kim, and 2 more authors

   IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Apr 2026

   Abs DOI

   Power side-channel (PSC) attacks exploit power consumption patterns to extract sensitive information, posing risks to cryptographic operations crucial for secure systems. Traditional countermeasures, such as masking, face challenges like complex synthesis integration, high area overhead, and vulnerability to optimization removal during logic synthesis. To address these issues, we introduce proposed side-channel aware synthesis (PoSyn), a novel logic synthesis framework designed to enhance cryptographic hardware’s resistance against PSC attacks. Our approach focuses on the optimal bipartite mapping of vulnerable register transfer level (RTL) components to standard cells from the technology library to minimize PSC leakage. By employing a cost function that integrates key characteristics from the RTL design and the standard cell library, we strategically modify the mapping criteria during the conversion of RTL designs into standard cell netlists without altering the design functionality. Furthermore, PoSyn is theoretically shown to minimize mutual information leakage, further reinforcing its security against PSC vulnerabilities. PoSyn is evaluated on a variety of cryptographic hardware, including AES, RSA, PRESENT, and postquantum cryptography algorithms like Saber and CRYSTALS-Kyber across 65-, 45-, and 15-nm nodes. Our experimental results demonstrate a significant reduction of success rates for differential power analysis (DPA) and correlation power analysis (CPA) attacks, as low as 3% and 6%, respectively. Furthermore, test vector leakage assessment (TVLA) confirms that the synthesized netlists exhibit negligible leakage. Moreover, compared to traditional countermeasures such as masking and shuffling, PoSyn achieves notably lowers the success rates, achieving a reduction by up to 72%, while simultaneously enhancing area efficiency by as much as 3.79\times . These results highlight the effectiveness of PoSyn in securing cryptographic hardware with minimal impact on area and performance.

2. CHoRD: Coordinating Scheduling and Data Placement for Efficient Deep Neural Network Inference on Chiplet-Based GPUs

   Hanpei Liu, Samit S. Miftah, Dipali Jain, and 4 more authors

   In Advances in Neural Information Processing Systems (NeurIPS), 2026

2025

1. SymbFuzz: Symbolic Execution Guided Hardware Fuzzing

   Samit Shahnawaz Miftah, Amisha Srivastava, Hyunmin Kim, and 2 more authors

   In Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture, , 2025

   Abs DOI

   Modern hardware incorporates reusable designs to reduce cost and time to market, inadvertently increasing exposure to security vulnerabilities. While formal verification and simulation-based approaches have been traditionally utilized to mitigate these vulnerabilities, formal techniques are hindered by scalability issues, while conventional simulation methods frequently overlook critical edge cases. Fuzzing, as a simulation-based strategy, has demonstrated considerable promise in enhancing the security of both software and hardware; however, it is impeded by challenges such as limited input coverage, difficulties in traversing branching paths, and the complexity of managing circuit parameters, in addition to the limited adaptability of existing hardware fuzzing techniques within industrial workflows. To address these limitations, we propose SymbFuzz, an innovative hybrid hardware fuzzing methodology that leverages symbolic execution to achieve superior coverage. SymbFuzz is the first hardware fuzzing technique to be implemented on the industry-standard Universal Verification Methodology (UVM), facilitating seamless integration into commercial hardware verification flows. SymbFuzz was evaluated on a diverse set of processor RTLs, including OpenTitan (Ibex), CVA6, Rocket-Core, and Mor1kx. These designs span a range of processor architectures and complexities. SymbFuzz detected all bugs previously found by existing fuzzers and additionally uncovered 14 new bugs, including a vulnerability in OpenTitan, reported in the CWE 2025 database. It also achieved up to 6.8 \texttimes faster convergence compared to traditional UVM random testing and over 2 \texttimes 104 additional functional coverage points compared to state-of-the-art fuzzers, demonstrating its effectiveness in improving RTL validation across varied processor architectures.

2. InterConFuzz: A Fuzzing-based Comprehensive NoC Verification Framework

   Samit Shahnawaz Miftah, Hyunmin Kim, and Kanad Basu

   In 2025 62nd ACM/IEEE Design Automation Conference (DAC), Jun 2025

   Abs DOI

   Security verification of Network-on-Chip (NoC) systems is essential due to their intricate and high-concurrency structures. Traditional methods often fail to cover all scenarios or scale effectively, leading to prolonged verification and overlooked vulnerabilities. Our proposed solution, InterConFuzz, a hybrid hardware fuzzing technique, uses symbolic execution for extensive coverage. Developed on Universal Verification Methodology (UVM), InterConFuzz discovered five security flaws in the NoC architecture of the OpenTitan SoC-surpassing existing techniques by three-while reducing memory and computational needs by 24.4% and 29.5%, respectively. Furthermore, InterConFuzz furnished comparable functional coverage compared to existing NoC fuzzing approaches, proving its efficiency and robustness.

3. OpenAssert: Towards Secure Assertion Generation using Large Language Models

   Anand Menon, Samit Shahnawaz Miftah, Amisha Srivastava, and 6 more authors

   In 2025 IEEE 43rd VLSI Test Symposium (VTS), Apr 2025

   Abs DOI

   Assertions are critical components used in hardware verification, ensuring robust functionality, fortifying design security, and providing essential verification features. Traditional hardware assertion methods are not automated, complicate security audits, and require effort, causing prolonged development cycles. Recent studies have highlighted the potential of commercial Large Language Models (LLMs) to generate security-focused assertions by leveraging textual data from design specifications. However, reliance on proprietary models like GPT-4 severely jeopardizes IP privacy and data confidentiality, undermining transparency and accountability in data handling practices. In this paper, we address secure hardware assertion generation by proposing a practical approach to significantly enhance the feasibility of open-source LLMs. Our proposed method, OpenAssert, involves fine-tuning existing models to be utilized locally at the user’s end without compromising confidentiality. Additionally, we employ Retrieval Augmentation Generation to refine these models, mitigating hallucinations and security-related errors. OpenAssert demonstrates improvements, achieving up to a 44% increase in rouge-1 score, a 49% improvement in cosine similarity, and a 43.4% reduction in word error rate for security-critical designs compared to open-source models.

4. Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Dataset

   Anand Menon, Samit Miftah, Shamik Kundu, and 7 more authors

   ACM Trans. Des. Autom. Electron. Syst., Aug 2025

   Just Accepted

   Abs DOI

   Hardware verification is crucial in modern SoC design, consuming around 70% of development time. SystemVerilog assertions ensure correct functionality. However, existing industrial practices rely on manual efforts for assertion generation, which becomes increasingly untenable as hardware systems become complex. Recent research shows that Large Language Models (LLMs) can automate this process. However, proprietary SOTA models like GPT-4o often generate inaccurate assertions and require expensive licenses, while smaller open-source LLMs need fine-tuning to manage HDL code complexities. To address these issues, we introduce VERT, an open-source dataset designed to enhance SystemVerilog assertion generation using LLMs. VERT enables researchers in academia and industry to fine-tune open-source models, outperforming larger proprietary ones in both accuracy and efficiency while ensuring data privacy through local fine-tuning and eliminating costly licenses. The dataset is curated by systematically augmenting variables from open-source HDL repositories to generate synthetic code snippets paired with corresponding assertions. Experimental results demonstrate that fine-tuned models like Deepseek Coder 6.7B and Llama 3.1 8B outperform GPT-4o, achieving up to 96.88% improvement over base models and 24.14% over GPT-4o on platforms including OpenTitan, CVA6, OpenPiton, and Pulpissimo. VERT is available at https://github.com/AnandMenon12/VERT.

5. Security Verification for Next-Generation SoCs

   Samit Shahnawaz Miftah, Amisha Srivastava, Yiorgos Makris, and 1 more author

   In Advances in Hardware Design for Security and Trust, 2025

   Abs DOI

   Modern system-on-chip (SoC) designs are gaining traction in computing system designs due to their ability to provide efficient, high-performance computing with minimal latency and power consumption. Furthermore, they streamline design processes and facilitate the integration of reusable intellectual properties (IPs). However, the integration of third-party IPs (3PIPs) in SoCs can inadvertently introduce security vulnerabilities exploitable by adversaries. The next generation of SoC design is moving towards a chiplet-based architecture that allows further reusability of IPs and enables heterogeneous integration of 3PIPs. This exacerbates the security risks in the SoC architectures. As the size and complexity of these next-generation SoCs grow, existing formal-based approaches struggle to scale for adequate security verification. To address this challenge, both industry and academia are exploring new verification methodologies such as concolic testing, fuzzing, and information flow tracking to meet the security needs of future SoCs. These approaches aim for efficient security verification by reducing search space, tracking specific data paths, or using feedback mechanisms while dynamically verifying the design under verification (DUV). This chapter explores the security challenges posed by next-generation SoC architectures, presents recent advancements aimed at overcoming these challenges, and outlines the future trajectory of security verification in this domain.

2024

1. Assert-O: Context-based Assertion Optimization using LLMs

   Samit Shahnawaz Miftah, Amisha Srivastava, Hyunmin Kim, and 1 more author

   In Proceedings of the Great Lakes Symposium on VLSI 2024, Clearwater, FL, USA, 2024

   Abs DOI

   Modern computing relies on System-on-Chips (SoCs), integrating IP cores for complex functions. However, this integration introduces vulnerabilities, necessitating rigorous hardware security validation. The effectiveness of this validation depends on the security properties embedded in the SoC. Recent studies explore large language models (LLMs) for generating security properties, but these may not be directly optimized for validation. Manual intervention remains necessary to reduce their number. Security validation methods that rely on human expertise are not scalable as they are time-intensive and prone to human error. In order to address these issues, we introduce Assert-O, an automated framework designed to derive security properties from SoC documentation and optimize the generated properties. It also ranks the properties based on the security vulnerabilities they are associated with, thereby streamlining the validation process. Our method leverages hardware documentation to initially create security properties, which are subsequently consolidated and prioritized based on their level of criticality. This approach serves to expedite the validation procedure. Assert-O is trained on documentation of six IPs from OpenTitan. To evaluate our proposed method, Assert-O was assessed on five other modules from OpenTitan. Assert-O was able to generate 183 properties, which was further optimized to reduce them to 138 properties. Subsequently, these properties were ranked based on their impact on the security of the overall system.

2. System-on-Chip Information Flow Validation Under Asynchronous Resets

   Samit S. Miftah, Kshitij Raj, Xingyu Meng, and 2 more authors

   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Sep 2024

   Abs DOI

   Modern system-on-chip (SoC) designs comprise hundreds of individual IP blocks, each with its custom implementation of reset signals in most cases. The asynchronous nature of these resets while crossing different reset domains makes the SoC prone to various vulnerabilities if not implemented and validated thoroughly. A key aspect in validating system functionality is to ensure the functionality under reset is verified. Traditional simulation-based validation techniques often become a bottleneck in complex SoC designs due to the large control path of these designs. We propose SoC security checker under asynchronous resets (SoCCAR), a SoC validation framework that addresses this problem. SoCCAR leverages control flow graphs (CFGs) of the design to extract the control flow associated with property violations caused by reset domain crossings due to asynchronous resets. SoCCAR efficiently tracks the chain of events leading to the payload without suffering from state space explosion, a common challenge in complex designs. We test the efficacy of SoCCAR in detecting such vulnerabilities by developing multiple SoC benchmarks, each embedded with custom vulnerability originating from reset implementations across different domains. These vulnerabilities reflect practical design complexity and correspond to security violations encountered in practice as a result of multiple asynchronous resets. SoCCAR successfully detected all violations with minimal computation overhead and runtime, making it a viable approach for detecting such violations in complex SoC designs.

3. RTL-Spec: RTL Spectrum Analysis for Security Bug Localization

   Samit S. Miftah, Shamik Kundu, Austin Mordahl, and 2 more authors

   In 2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2024

   Abs DOI

   Modern System-on-Chip (SoC) designs are integrated with intellectual property (IPs) cores to achieve complex functionalities. While this integration significantly improves the computing power of SoCs, it also leads to an increase in verification complexity pertaining to the security of the SoC design. Existing SoC verification techniques do not offer localization capability to pinpoint the root causes of security vulnerabilities in the register transfer level (RTL) code. This leads to significant delay, incurred due to SoC debugging. Fault localization techniques, such as spectrum-based methodologies, are used predominantly in software validation and testing to debug and localize bugs in programs. However, due to the absence of any such techniques that correlate faulty output with individual lines of RTL code, approaches that can detect vulnerabilities in the hardware have not yet been adopted. In order to circumvent this, in this paper, we, for the first time, propose RTL-Spec, a RTL level security vulnerability localization framework that aims to pinpoint buggy lines in the RTL code to ensure the security of the SoC design in its pre-silicon phase. RTL-Spec achieves this by establishing a correlation between the effects of input patterns in simulation runs and the corresponding statements in the RTL code. The subsequent stage employs a spectrum-based localization technique to identify buggy statements in RTL that might cause vulnerabilities. The efficacy of RTL-Spec was assessed using a buggy version of PULPissimo SoC, utilized in the “Hack @DAC2018” competition. RTL-Spec accurately identified the origin of all 14 vulnerabilities in the RTL code and achieved a precision of 100 % in 10 out of the 14 cases.

2019

1. Image Encryption and Decryption using Enigma Algorithm

   Md. Towsif Abir, Lamiya Rahman, Samit Shahnawaz Miftah, and 3 more authors

   In 2019 IEEE International Conference on Electrical, Computer and Communication Technologies (ICECCT), Feb 2019

   Abs DOI

   The main objective of this paper is to present a more secured and computationally efficient procedureof encrypting and decrypting images using the enigma algorithm in comparison to the existing methods. Available literature on image encryptions and descriptionsare not highly secured in every case.To achieve more secured image processing for highly advanced technologies, a proposed algorithm can be theprocess used in enigma machine for image encryption and decryption. Enigma machine is piece of spook hardware that was used frequently during the World War II by the Germans. This paper describes the detailed algorithm along with proper demonstration of several essential components present in an enigma machine that is required for image security. Each pixel in a colorful picture can be represented by RGB (Red, Green, Blue) value. The range of RGB values is 0 to 255 that states the red, green and blue intensity of a particular picture.These RGB values are accessed one by one and changed into another by various steps and hence it is not possible to track the original RGB value. In order to retrieve the original image, the receiver needs to know the setting of the enigma. To compare the decrypted image with the original one,these two images are subtracted and their results are also discussed in this paper.

2. Image Processing Method for Measurement of Refractive Index

   Samit Shahnawaz Miftah, Md. Towsif Abir, Md. Sazzad Hossain, and 2 more authors

   In 2019 IEEE International Conference on Electrical, Computer and Communication Technologies (ICECCT), Feb 2019

   Abs DOI

   This paperproposes a method for determining the refractive index of a material. The proposed method is based on image processing. The method uses twoimagestaken from an experimental setup. The first one is of a laser beam focused on a plane withthe presence of the concerned material and the second one without it.The refractive index is then determined by processing those images with MATLAB. This method is quicker and cheaper for the determination of the refractive index within a range of ±3.5% of permissible error.